The present invention relates to a control mechanism for an instruction pipe in a processor that maintains timing synchronism between the instruction pipe and other elements outside the instruction pipe.
Execution logic in modern processors have begun to incorporate multiple instruction pipes. Each instruction pipe may include sufficient circuitry to execute most program instructions independently of the other pipes. Thus, a processor having multiple instruction pipes may perform nearly perfect parallel execution of program instructions.
It may not be desirable for instruction pipes to operate with complete independence from each other. For certain operations, greater efficiencies may be achieved by having the instruction pipes share access to other logic circuits. By way of example, it may be preferable for multiple instruction pipes to share a single Return Stack Buffer (“RSB”). As is known, an RSB is a buffer that stores forward and return pointers associated with call and return instructions. When a processor executes a call, it pushes an address associated with the call instruction to the RSB, typically the address of an instruction immediately following the call instruction, and begins execution at another program instruction at an address specified in the body of the call instruction. When a processor executes a return instruction, it retrieves an address from the top of the RSB and commences program execution at the retrieved address. Even in a processor having multiple instruction pipes, it may be more efficient to provide a single RSB for all instruction pipes rather than to provide a separate RSB for each of the instruction pipes. Because RSBs typically are not used every clock cycle, sharing the RSB improves utilization and reduces cost over a double-RSB design, for example.
In one implementation, an RSB may be provided within a first instruction pipe. Other instruction pipes in the processor may communicate with the RSB to store addresses therein for call instructions or to retrieve addresses therefrom for return instructions. However, this implementation raises a variety of timing problems.
A first timing problem arises because one RSB must be shared among a variety of instruction pipes. For N instruction pipes in a processor, each instruction pipe may enjoy utilization of the RSB reduced on a pro rata basis (1/Nth of the RSB's total capacity). If an instruction pipe issues read or write requests to the RSB in excess of its pro rata share, the requests may be dropped. This would result in processor failure.
A second timing problem may arise due to round-trip communication latencies between an instruction pipe and the RSB. Requests must propagate from an instruction pipe to an RSB, be acted upon by the RSB and results therefrom must return to the instruction pipe. An instruction pipe that does not account for this round-trip latency during operation may act upon invalid data. Again, this would result in processor failure.
Accordingly, there is a need in the art for a timing control mechanism for use in instruction pipes to conform operation of the instruction pipe to timing limitations that may arise when interfacing the instruction pipe with external elements.